Ikos Pegasus reverse engineering
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= Interconnect =
= Interconnect =
reverse engineering of the interconnect can be vastly automated by using techniques such as that of [http://nsa.unaligned.org NSA@home].
== FPGA to FPGA ==
== FPGA to FPGA ==
Revision as of 21:11, 11 August 2010
A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are many of them, brute forcing designs can be usually deeply pipelined to make them fast even on slow FPGAs, and it is a great learning tool.
- The rack with the power supply can hold up to 7 boards connected via a backplane.
- One main board with:
- SCSI controller
- 5 auxiliary boards with (each):
- 1 XC95216 CPLD
- 64 XC4036XL FPGAs
- lots of SRAM
- One auxiliary board was destructively reverse engineered, so only 4 are remaining.
Some device photos are here.
See also business articles about the product and its manufacturer:
- Mentor Graphics to buy Ikos Systems for 1.69 times revenue
- IKOS' VirtuaLogic Emulator Breaks DesignCompilation Time Speed Barrier
- Rendition Selects VirtuaLogic Emulator
There are also some reports of using the device in academia, many papers are available from the I€€€ if you have some grease money to spare.
Programming the auxiliary boards
In normal operation, the CPLD receives configuration data from the backplane (originating from the mainboard through the SCSI port) and distributes it to the FPGAs. The CPLD uses JTAG to send data to the FPGAs. The 64 FPGAs on each auxiliary board are arranged to form one big JTAG chain driven by the CPLD.
Because this mode of operation uses a proprietary protocol which is especially hard to reverse engineer since we do not have the original software and SCSI device driver, we are trying to program the boards with a JTAG probe.
The CPLD's JTAG port is accessible on each board with a HE10 connector following the MultiLINX pinout.
Legend: X = missing pin (key), NC = No Connect
We can use urJTAG to access the CPLD, with the BSDL files released by Xilinx to enable boundary scan. For an unknown reason, the Xilinx iMPACT tool fails to recognize the CPLD.
How to use boundary scan with urJTAG
cable xpc_ext bsdl path [path to BSDL files] detect instruction EXTEST shift ir set signal [pin name from BSDL] out 1 shift dr
FPGA JTAG chain topology
All the 64 FPGAs are arranged in a daisy chain for TDI and TDO.
For TCK and TMS, the board is divided into 4 quadrants and these signals are shared within each quadrant.
Connection of the FPGA JTAG chain to the CPLD
TCK and TMS are not directly connected to the CPLD, but go through a column of 74xx244 TTL buffers in the middle of the board. TDI and TDO are directly connected to the CPLD.
Each auxiliary board has 2 LEDs in the front. They are connected to CPLD pins 58 and 86 in current sink (active low) mode. They can be useful to test your CPLD boundary scan setup.
You will need to use Synplify which supports the XC4000 family of FPGAs. There is no Xst support whatsoever.
Place and route
Synplify generates an EDIF netlist which can be fed to the ISE Classics tools for place and route and bitstream generation.
FPGA JTAG programming
- JTAG tunnelling through the CPLD boundary scan?
- or reprogram the CPLD to re-route JTAG somewhere else?
- does iMPACT support XC4000s?
- it seems urJTAG has some FPGA programming support.
Once we have full JTAG access to the FPGAs, the reverse engineering of the interconnect can be vastly automated by using techniques such as that of NSA@home.
FPGA to FPGA
FPGA to SRAM
FPGA to I/O port
Board to board