Ikos Pegasus reverse engineering

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Device overview

  • One main board with SCSI controller, 8051, CPLD, some FPGAs and SDRAM.
  • 5 auxiliary boards with (each):
    • 1 XC95216 CPLD
    • 64 XC4036 FPGAs
    • lots of SRAM
  • One auxiliary board was destructively reverse engineered, so only 4 are remaining.

Programming the auxiliary boards

In normal operation, the CPLD receives configuration data from the backplane (originating from the mainboard through the SCSI port) and distributes it to the FPGAs. The CPLD uses JTAG to send data to the FPGAs. The 64 FPGAs on each auxiliary board are arranged to form one big JTAG chain driven by the CPLD.

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