Ikos Pegasus reverse engineering
- The rack with the power supply can hold up to 7 boards connected via a backplane.
- One main board with:
- SCSI controller
- 5 auxiliary boards with (each):
- 1 XC95216 CPLD
- 64 XC4036XL FPGAs
- lots of SRAM
- One auxiliary board was destructively reverse engineered, so only 4 are remaining.
Some device photos are here.
Programming the auxiliary boards
Because this mode of operation uses a proprietary protocol which is especially hard to reverse engineer since we do not have the original software and SCSI device driver, we are trying to program the boards with a JTAG probe.
The CPLD's JTAG port is accessible on each board with a HE10 connector following the MultiLINX pinout.
Legend: X = missing pin (key), NC = No Connect
We can use urJTAG to access the CPLD, with the BSDL files released by Xilinx to enable boundary scan. For an unknown reason, the Xilinx iMPACT tool fails to recognize the CPLD.
How to use boundary scan with urJTAG
cable xpc_ext bsdl path [path to BSDL files] detect instruction EXTEST shift ir set signal [pin name from BSDL] out 1 shift dr
FPGA JTAG chain topology
All the 64 FPGAs are arranged in a daisy chain for TDI and TDO.
For TCK and TMS, the board is divided into 4 quadrants and these signals are shared within each quadrant.
Connection of the FPGA JTAG chain to the CPLD
TCK and TMS are not directly connected to the CPLD, but go through a column of 74xx244 TTL buffers in the middle of the board. TDI and TDO are directly connected to the CPLD.
Each auxiliary board has 2 LEDs in the front. They are connected to CPLD pins 58 and 86 in current sink (active low) mode. They can be useful to test your CPLD boundary scan setup.
The reverse engineering of the interconnect can be vastly automated by using techniques such as that of NSA@home.
FPGA to FPGA
FPGA to SRAM
FPGA to I/O port
Board to board