Ikos Pegasus reverse engineering - Revision history

Zilking75: /* CPLD access */

2012-01-12T05:02:45Z

‎CPLD access

Zilking75: /* Situation */

2012-01-05T05:10:30Z

‎Situation

Zilking75: /* What? */

2012-01-02T15:17:31Z

‎What?

MacyWales at 04:28, 20 December 2011

2011-12-20T04:28:19Z

MacyWales at 03:14, 16 December 2011

2011-12-16T03:14:01Z

Lekernel: /* What? */

2011-05-04T10:25:35Z

‎What?

Aeris: /* How to use boundary scan with urJTAG */

2011-02-24T08:59:36Z

‎How to use boundary scan with urJTAG

Aeris: Undo revision 2850 by Aeris (Talk)

2010-10-28T11:10:23Z

Undo revision 2850 by Aeris (Talk)

Aeris: /* What? */

2010-10-28T11:09:39Z

‎What?

Lekernel: /* Connection of the FPGA JTAG chain to the CPLD */

2010-08-14T16:40:47Z

‎Connection of the FPGA JTAG chain to the CPLD

@@ Line 82: / Line 82: @@
 Legend: X = missing pin (key), NC = No Connect
-We can use [http://urjtag.org urJTAG] to access the CPLD, with the BSDL files released by Xilinx to enable boundary scan. For an unknown reason, the Xilinx iMPACT tool fails to recognize the CPLD.
+We can use [http://urjtag.org urJTAG] to access the CPLD, with the BSDL files released by Xilinx to enable boundary scan. For an unknown reason, the Xilinx iMPACT tool fails to recognize the <span class="plainlinks">[http://www.great-quotes.com/quotes/author/Audrey/Hepburn<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">Audrey Hepburn quotes</span>] CPLD.
 === How to use boundary scan with urJTAG ===

@@ Line 34: / Line 34: @@
 In normal operation, the CPLD receives configuration data from the backplane (originating from the mainboard through the SCSI port) and distributes it to the FPGAs. The CPLD uses JTAG to send data to the FPGAs. The 64 FPGAs on each auxiliary board are arranged to form one big JTAG chain driven by the CPLD.
-Because this mode of operation uses a proprietary protocol which is especially hard to reverse engineer since we do not have the original software and SCSI device driver, we are trying to program the boards with a JTAG probe.
+Because this mode of operation uses a proprietary protocol which is especially hard to reverse engineer since we do not have the original software and SCSI device driver, we are trying to program the <span class="plainlinks">[http://540seo.com/<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">local search engine optimization</span>] boards with a JTAG probe.
 == FPGA JTAG pins ==

@@ Line 1: / Line 1: @@
 = Overview =
 == What? ==
-A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make <span class="plainlinks">[http://www.andrewflusche.com/services/spotsylvania-reckless-driving-defense/<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">Spotsylvania reckless driving</span>] them fast even on slow FPGAs, and it is a great <span class="plainlinks">[http://www.culinarydepotinc.com<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">restaurant supplies</span>] learning tool.
+A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make <span class="plainlinks">[http://www.premierrivercruises.com/river-cruise-regions-of-the-world/france-river-cruises<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">river cruises in france</span>] <span class="plainlinks">[http://www.andrewflusche.com/services/spotsylvania-reckless-driving-defense/<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">Spotsylvania reckless driving</span>] them fast even on slow FPGAs, and it is a great <span class="plainlinks">[http://www.culinarydepotinc.com<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">restaurant supplies</span>] learning tool.
 * The rack with the power supply can hold up to 7 boards connected via a backplane.

@@ Line 1: / Line 1: @@
 = Overview =
 == What? ==
-A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make <span class="plainlinks">[http://www.andrewflusche.com/services/spotsylvania-reckless-driving-defense/<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">Spotsylvania reckless driving</span>] them fast even on slow FPGAs, and it is a great learning tool.
+A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make <span class="plainlinks">[http://www.andrewflusche.com/services/spotsylvania-reckless-driving-defense/<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">Spotsylvania reckless driving</span>] them fast even on slow FPGAs, and it is a great <span class="plainlinks">[http://www.culinarydepotinc.com<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">restaurant supplies</span>] learning tool.
 * The rack with the power supply can hold up to 7 boards connected via a backplane.

@@ Line 1: / Line 1: @@
 = Overview =
 == What? ==
-A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make them fast even on slow FPGAs, and it is a great learning tool.
+A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make <span class="plainlinks">[http://www.andrewflusche.com/services/spotsylvania-reckless-driving-defense/<span style="color:black;font-weight:normal; text-decoration:none!important; background:none!important; text-decoration:none;">Spotsylvania reckless driving</span>] them fast even on slow FPGAs, and it is a great learning tool.
 * The rack with the power supply can hold up to 7 boards connected via a backplane.

← Older revision		Revision as of 10:25, 4 May 2011
Line 24:		Line 24:

	There are also some reports of using the device in academia, many papers are available from the [http://www.ieeesucks.com I€€€] if you have some grease money to spare.		There are also some reports of using the device in academia, many papers are available from the [http://www.ieeesucks.com I€€€] if you have some grease money to spare.
		+
		+	Some hints about the original software here: http://groups.csail.mit.edu/cag/raw/benchmark/include/vmw/interface/slic/driver/

	== Who? ==		== Who? ==

@@ Line 83: / Line 83: @@
 === How to use boundary scan with urJTAG ===
    cable xpc_ext
    bsdl path [path to BSDL files]
    detect

@@ Line 3: / Line 3: @@
 A big FPGA based ASIC emulator from the late 90s. Hundreds of FPGAs, thousands of I/Os, hundreds of amperes, dozens of kilos, etc. The FPGAs are quite old (approx. 1/3 the size and 1/3 the speed of a Virtex4 XC4VLX25) but there are ''many'' of them, brute forcing designs can be usually deeply pipelined to make them fast even on slow FPGAs, and it is a great learning tool.
-* The rack with the power supply can hold up to 6 boards connected via a backplane.
+* The rack with the power supply can hold up to 7 boards connected via a backplane.
 * One main board with:
 ** SCSI controller

@@ Line 146: / Line 146: @@
 |TBD
 |}
 == LEDs ==